To reduce the number of internal components and the degradation of the read signal, many memory devices lack dedicated pass-gate transistors to couple and uncouple the read circuits, which each typically include a sense amplifier, equilibrate circuit, and a data-line driver, to and from the read lines during a read cycle and a write cycle respectively. Typically, in such a memory device, the column-select transistors that are used to connect the bit lines to the read lines also isolate the read circuits from the bit lines when the sense amplifier is enabled or clocked. Often, such a memory device couples both the read and the write lines to the bit lines of an addressed memory cell during both a read and a write cycle. Thus, the memory device often couples the read circuits to the write lines during a write cycle. Such coupling, however, typically does not affect the reading of data from or the writing of data to the memory cell.
A problem with such a memory device is that during a write cycle, the data-line drivers, which the memory device does not use during a write cycle, may draw a current, often called a "crowbar" current, from the power supply. A data-line driver acts as an interface between a read line and a data line of the data bus. During a read cycle, the sense amplifier amplifies the data signal from the addressed memory cell, and provides the amplified data signal on the read line. The data-line driver receives the amplified data signal on the read line and provides it to the data line. During a write cycle, the data-line driver ideally uncouples the read line from and presents a high impedance to the data line while drawing little or no supply current. During a write cycle, however, the transistor that couples the read line to the bit line of the addressed memory cell often generates on the read line a body-effected threshold voltage that is between a logic 0 (typically 0 volts) and a logic 1 (typically 5 volts). This body-effected threshold voltage is often sufficient to partially activate the input stage of the data-line driver, and thus cause the data-line driver to draw a supply current. The sum of such currents from all of the partially activated data-line drivers can be significant.
The sum of these crowbar currents may be sufficient to render such a memory device unsuitable for low-power applications, such as battery applications. Furthermore, the additional heat that these currents generate may shorten the lifetime of the memory device, or necessitate more complicated heat dissipation techniques or structures. Moreover, during stressing of the memory device, a higher-than normal power-supply voltage is applied to hasten the bum in of the memory device. For example, in a memory device that normally operates with a 5-volt supply, a 9-volt supply is used during stressing. Thus, because they may be even larger than during normal operation of the memory device, the crowbar currents may cause more severe heating problems or other problems during stress testing of the memory device.